The present invention relates to bit error rate testing, and more particularly, the present invention relates to bit error rate testing using programmable logic devices.
The input/output throughput of programmable logic devices, as well as other types of integrated circuits, is currently on the order of gigabits per second and continues to rise. With this high rate of data throughput, an area of concern arises with regard to bit error rate. The higher the bit error rate of a particular device, then the more bits need to be retransmitted, thus decreasing the overall data transfer rate. This clearly makes inefficient the high throughput rates of some of these devices when a high bit error rate is present.
It therefore becomes important to be able to gauge the bit error rate of any particular device or type of device. Knowing the bit error rate of devices allows designers and engineers to choose appropriate devices that are required to exhibit a particular (e.g., minimum) data transfer rate for a particular design or application.
Bit error rates are typically ascertained through the use of a bit error rate tester. Known bit error rate testers are typically expensive dedicated external equipment that is connected to the device to be tested. Vendors such as Agilent Technologies of Palo Alto, Calif. manufacture and market such bit error rate testers. Bit error rate measurement using such equipment may require on the order of days to complete. For example, it takes nearly four days to verify a bit error rate of 10E-14 (i.e., one error in 10E14 bits on average) at a 3 gigabit per second data rate.
It would therefore be desirable to provide a more efficient bit error rate tester for verifying the bit error rate of programmable logic devices.